![]() ![]() ![]() The instruction execution cycle consists of: The above-mentioned 15 steps are required to accomplish the task defined by the instruction: mov BYTE PTR ds:, 45h. The data byte 45h enters into the DSM location: 03010h. The CM sends data write signal to the memory chip. The contents of TRB8 (45) is placed on the DBUS.ġ5. The resultant address is asserted on the ABUS.ġ4. The content of ds, bx and TRA8 are added together to get the destination memory address as: 03010h. The data byte 45h comes from the CSM and then enters into the TRB8 of U7.ġ3. The CM increments the PC, which is now 01003h. The data 10h (8-bit displacement) enters into the DAR from where it enters into TRA8 of U7.ġ0. ![]() The CM increments the PC, which is now 01002h. Addressing Mode is determined as ‘Immediate’, which means that the last information byte (45) is the data for the destination.ħ. Therefore, two more read operations must be carried out to bring the remaining two byes (10 45) information from the memory. The opcodes ‘C6 47’ are jointly decoded and the CM extracts the following information: The opcode 47 (content of the memory location 01001h) enters into opcode decoder. The CM increments the PC, which is now 01001h. The opcode is interpreted and the CM understands that current instruction has an opcode of two bytes long.Ĥ. The opcode C6 (content of CSM memory location 01000h) enters into the opcode decoder. The CM (Control Matrix, U4) sends the RD/-signal to the memory chip.ģ. The PC (Program Counter, U1) asserts the address 01000h on the address bus.Ģ. Figure-2.45: Explaining Fetch-Execution Mechanism of ‘mov BYTE PTR ds:, 45h’ Instructionġ. ![]()
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